NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Collections About News Help Login

Press Enter or click the Search button to begin your search.

Back to Results
Hardware Verification at Computational Logic, IncThe following topics are covered in viewgraph form: (1) hardware verification; (2) Boyer-Moore logic; (3) core RISC; (4) the FM8502 fabrication, implementation specification, and pinout; (5) hardware description language; (6) arithmetic logic generator; (7) near term expected results; (8) present trends; (9) future directions; (10) collaborations and technology transfer; and (11) technology enablers.
Document ID
19910008258
Acquisition Source
Legacy CDMS
Document Type
Presentation
Authors
Bishop C Brock (Computational Logic Austin, Texas, United States)
Warren A Hunt, Jr (Computational Logic Austin, Texas, United States)
Date Acquired
September 6, 2013
Publication Date
November 1, 1990
Publication Information
Publication: NASA Formal Methods Workshop, 1990
Publisher: National Aeronautics and Space Administration
Subject Category
Computer Programming and Software
Report/Patent Number
NASA-CP-10052
Meeting Information
Meeting: NASA Formal Methods Workshop
Location: Hampton, VA
Country: US
Start Date: August 20, 1990
End Date: August 23, 1990
Sponsors: National Aeronautics and Space Administration
Accession Number
91N17571
Distribution Limits
Public
Copyright
Portions of document may include copyright protected material.
Technical Review
Single Expert

Related Records

IDRelationTitle19910008246Collected WorksNASA Formal Methods Workshop, 1990
No Preview Available