NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Press Enter or click the Search button to begin your search.

Back to Results
Analog VLSI neural network integrated circuitsTwo analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.
Document ID
19920013198
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Kub, F. J.
(Naval Research Lab. Washington, DC, United States)
Moon, K. K.
(Naval Research Lab. Washington, DC, United States)
Just, E. A.
(Naval Research Lab. Washington, DC, United States)
Date Acquired
September 6, 2013
Publication Date
December 1, 1991
Publication Information
Publication: NASA, Washington, Technology 2001: The Second National Technology Transfer Conference and Exposition, Volume 1
Subject Category
Electronics And Electrical Engineering
Accession Number
92N22441
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
No Preview Available