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Design and scheduling for periodic concurrent error detection and recovery in processor arraysPeriodic application of time-redundant error checking provides the trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. We derive the optimal scheduling of checking patterns in order to uniformly distribute the available checking capability and maximize the error coverage. Synchronous buffering designs using data forwarding and dynamic reconfiguration are described. Efficient single-cycle diagnosis is implemented by error pattern analysis and direct-mapped recovery cache. A rollback recovery scheme using start-up control for local recovery is also presented.
Document ID
19920020452
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Wang, Yi-Min
(Illinois Univ. Urbana, IL, United States)
Chung, Pi-Yu
(Illinois Univ. Urbana, IL, United States)
Fuchs, W. Kent
(Illinois Univ. Urbana, IL, United States)
Date Acquired
September 6, 2013
Publication Date
May 22, 1992
Subject Category
Computer Programming And Software
Report/Patent Number
UILU-ENG-92-2214
CRHC-92-08
NAS 1.26:190571
NASA-CR-190571
Report Number: UILU-ENG-92-2214
Report Number: CRHC-92-08
Report Number: NAS 1.26:190571
Report Number: NASA-CR-190571
Accession Number
92N29695
Funding Number(s)
CONTRACT_GRANT: N00014-90-J-1270
CONTRACT_GRANT: NAG1-613
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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