Hierarchical simulation of large system

The main problem facing current CAD tools for VLSIs is the large amount of memory required when dealing with large systems, primarily due to the circuit representation used by most current tools. This paper discusses an approach for hierarchical switch-level simulation of digital circuits. The approach exploits the hierarchy to reduce the memory requirements of the simulation, allowing the simulation of circuits that are too large to simulate at one flat level. The approach has been implemented in a hierarchical switch-level simulator, CHAMP, which runs on a SUN workstation. The program performs mixed mode simulation: parts of the circuit can be simulated faster at a behavioral level by supplying a high level software description. CHAMP allows assignable delays, and bidirectional signal flow inside circuit blocks that are represented as transistor networks as well as across the boundaries of higher level blocks. CHAMP is also unique in that it simulates directly from the hierarchical circuit description without flattening to a single level.