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Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatmentThin film ferroelectric capacitors comprising a ferroelectric film sandwiched between electrodes for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode. The anneal is done so as to form the interface between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550 to 600 C for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the nonswitching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the nonswitching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.
Document ID
19930008088
Acquisition Source
Legacy CDMS
Document Type
Other - Patent Application
Authors
Thakoor, Sarita
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
September 6, 2013
Publication Date
October 20, 1992
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NAS 1.71:NPO-18551-1-CU
Patent Number: NASA-CASE-NPO-18551-1-CU
Patent Application Number: US-PATENT-APPL-SN-963974
Report Number: NAS 1.71:NPO-18551-1-CU
Accession Number
93N17277
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
NASA-CASE-NPO-18551-1-CU
Patent Application
US-PATENT-APPL-SN-963974
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