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Method of Implementing Digital Phase-Locked LoopsIn a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, and root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (B(sub L)T approaches 0) and in a discrete-update formulation with arbitrary B(sub L)T. Deficiencies of the continuous-update approximation in large-B(sub L)T applications are avoided in the new discrete-update formulation.
Document ID
19970017009
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Stephens, Scott A.
(NASA Pasadena Office CA United States)
Thomas, J. Brooks
(NASA Pasadena Office CA United States)
Date Acquired
August 17, 2013
Publication Date
February 11, 1997
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Number: US-Patent-5,602,883
Patent Application Number: US-Patent-Appl-SN-141797
Patent Number: NASA-Case-NPO-18757-1-CU
Accession Number
97N19376
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-5,602,883|NASA-Case-NPO-18757-1-CU
Patent Application
US-Patent-Appl-SN-141797
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