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A Systematic Methodology for Verifying Superscalar MicroprocessorsWe present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function by using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding the term size and case explosion problem that limits the pure flushing approach, our method helps localize errors, and also handles stages with interactive loops. The technique is illustrated on pipelined and superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution.
Document ID
19990018275
Acquisition Source
Langley Research Center
Document Type
Contractor Report (CR)
Authors
Srivas, Mandayam
(SRI International Corp. Menlo Park, CA United States)
Hosabettu, Ravi
(Utah Univ. Salt Lake City, UT United States)
Gopalakrishnan, Ganesh
(Utah Univ. Salt Lake City, UT United States)
Date Acquired
September 6, 2013
Publication Date
February 1, 1999
Subject Category
Computer Programming And Software
Report/Patent Number
NASA/CR-1999-208991
NAS 1.26:208991
Report Number: NASA/CR-1999-208991
Report Number: NAS 1.26:208991
Funding Number(s)
CONTRACT_GRANT: NAS1-20334
PROJECT: RTOP 519-50-11-01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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