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A Parallel Genetic Algorithm for Automated Electronic Circuit DesignParallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.
Document ID
20000064580
Document Type
Conference Paper
Authors
Long, Jason D. (NASA Ames Research Center Moffett Field, CA United States)
Colombano, Silvano P. (NASA Ames Research Center Moffett Field, CA United States)
Haith, Gary L. (NASA Ames Research Center Moffett Field, CA United States)
Stassinopoulos, Dimitris (NASA Ames Research Center Moffett Field, CA United States)
Date Acquired
August 19, 2013
Publication Date
February 1, 2000
Publication Information
Publication: Welcome to the NASA High Performance Computing and Communications Computational Aerosciences (CAS) Workshop 2000
Subject Category
Computer Programming and Software
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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IDRelationTitle20000064579Analytic PrimaryWelcome to the NASA High Performance Computing and Communications Computational Aerosciences (CAS) Workshop 2000
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