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Characterization of a New EEPROM/Flash Memory CellThis paper discusses on-going work sponsored through the Defense Threat Reduction Agency (DTRA) SBIR program at Peregrine Semiconductor Corp to characterize the radiation and endurance performance characteristics of Peregrine's patented PlusCell(TM) - a new non-volatile memory cell which utilizes a standard CMOS process on a silicon on insulator technology. This work begins with basic cell characterization of write voltages & read currents on sample cells across multiple wafer lots, progresses through cell retention and endurance testing across temperature and radiation environment, extracting necessary activation energy for cell charge leakage and completes with total dose characterization of the basic cell through 100 K write/erase cycles with radiation testing performed after 0, 10 K & 100 K write/erase cycles. The PlusCell(TM) is very compact and operates at write voltages as low as 6 V and read voltages below 1 V. Charge injection of both polarities is accomplished through a 100 A thick gate oxide by means of hot carrier injection. The cell relies on isolation provided by an insulating substrate. In the case of Peregrine's UTSi technology, the base technology is fully depleted silicon on sapphire CMOS and the cell is manufactured without any additional processing or masking steps. Measured cell performance of charge retention, radiation sensitivity and endurance is presented. Traditional EEPROM or flash cells require specialized regions of thin tunneling oxide, which increase complexity and cost while reducing density and yield. Additionally, the normal injection mechanism is based only on electrons, which means writing and erasing must be carefully balanced, or over-erasing can occur. The PlusCell(TM) using both hole and electron injection, has several key advantages including elimination of any over-erase mechanism, an extremely dense cell, availability of bi-directional read, and efficient block erase.
Document ID
20020043709
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
Authors
Ron Reedy
(Peregrine Semiconductor Corporation San Diego, CA United States)
Jim Cable
(Peregrine Semiconductor Corporation San Diego, CA United States)
Frank Wright
(Peregrine Semiconductor Corporation San Diego, CA United States)
Hal Anthony
(Peregrine Semiconductor Corporation San Diego, CA United States)
Chuck Tabbert
(Peregrine Semiconductor Corporation San Diego, CA United States)
Date Acquired
August 20, 2013
Publication Date
November 1, 2000
Publication Information
Publication: Non-Volatile Memory Technology Symposium 2000: Proceedings
Publisher: Jet Propulsion Laboratory
Subject Category
Electronics and Electrical Engineering
Report/Patent Number
JPL-Publ-00-15
Meeting Information
Meeting: Non-Volatile Memory Technology Symposium 2000
Location: Arlington, VA
Country: US
Start Date: November 15, 2000
End Date: November 16, 2000
Sponsors: Jet Propulsion Laboratory
Distribution Limits
Public
Copyright
Public Use Permitted.
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