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Ka-Band Wide-Bandgap Solid-State Power Amplifier: Prototype Combiner Spurious Mode Suppression and Power ConstraintsResults of prototype hardware activities related to a 120-W, 32-GHz (Ka-band) solid-state power amplifier (SSPA) architecture study are presented. Spurious mode suppression and the power-handling capability of a prototype 24-way radial combiner and a prototype 2-way septum binary combiner were investigated. Experimental data indicate that a commercial absorptive filter, designed to pass the circular TE01 mode, effectively suppressed the higher-order modes generated by a narrowband, flower-petal-type mode transducer. However, the same filter was not effective in suppressing higher-order modes generated by the broadband Marie mode transducer that is used in the prototype waveguide radial combiner. Should greater filtering be required by a particular SSPA application, a broadband mode filter that can suppress specifically those higher-order modes that are generated by the Marie transducer will need to be developed. A back-to-back configuration of the prototype radial combiner was tested with drive power up to approximately 50 W. No anomalous behavior was observed. Power measurements of the septum combiner indicate that up to 10-W radio frequency (RF) can be dissipated in the integrated resistive element before a permanent performance shift is observed. Thus, a given adder (a single-stage, 2-way combiner) can safely combine two 20-W sources, and the adder will not be damaged in the event of a source failure. This result is used to calculate the maximum source power that can be safely combined as a function of the number of sources combined and the number of source failures allowed in a multi-stage combiner. The analysis shows that SSPA power >140 W can be generated by power combining 16 sources producing 10 W each. In this configuration, up to three sources could fail with the guarantee that the combiner would not be damaged. Finally, a modified prototype septum combiner design was verified. The improved design reduced the assembly time from over 2 hours to about 15 minutes per adder.
Document ID
20060008609
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other
Authors
Khan, P.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Epp, L.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
September 7, 2013
Publication Date
February 15, 2006
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
IPN-PR-42-164
Report Number: IPN-PR-42-164
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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