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CMOS digital imager design from a system-on-a-chip perspective
In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip.
Document ID
20060030414
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/10984
Authors
Pain, B.
Hancock, B.
Cunningham, T.
Yang, G.
Seshadri, S.
Heynssens, J.
Wrigley, C.
Date Acquired
August 23, 2013
Publication Date
January 4, 2000
Subject Category
Electronics And Electrical Engineering
Distribution Limits
Public
Copyright
Other
Keywords
CMOS imager noise
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