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Assembly and Cleaning of CSPs for High, Low, and UltraLow Volume ApplicationsThe JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Document ID
20060032177
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/13647
Authors
Ghaffarian, R.
Mehta, A.
Bonner, J.
Achong, C.
Vogler, O.
Phillips, D.
Celestica, A.
Mehrotra, M.
Simeus, M.
Stegura, S.
Date Acquired
August 23, 2013
Publication Date
November 14, 2000
Distribution Limits
Public
Copyright
Other
Keywords
electronic assembly SMT chip scale package CSP solder volume fine pitch

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