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The Design Process of an Evolutionary Oriented Reconfigurable ArchitectureThis paper describes the design of a reconfigurable chip programmable at the transistor level and oriented to the implementation of Evolvable Hardware (EHW) experiements.
Document ID
20060033107
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/15695
Authors
Zebulum, R.
Stoica, A.
Keymeulen, D.
Date Acquired
August 23, 2013
Publication Date
July 13, 2000
Distribution Limits
Public
Copyright
Other
Keywords
evolvable hardware reconfigurable hardware genetic algorithms FPAA FPGA

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