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3D Chip Scale Package (CSP)Package/die stacking technology enhances most aspects of electronic systems such as size, weight, speed, yield, and power consumption.
Document ID
20060034020
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
hdl:2014/17367
Authors
Ghaffarian, R.
Date Acquired
August 23, 2013
Publication Date
January 1, 1999
Publication Information
Publication: Chip Scale Packaging for Modern Electronics
Distribution Limits
Public
Copyright
Other
Keywords
Chip Scale Packaging (CSP) 3D CSP Stack TSOP D2CSP MCP Fine Pitch BGA FPBGA

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