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Concurrent Processor Array for High Speed Route PlanningA VLSI parallel processor array for high speed optimal route planning is reported.
Document ID
20060037827
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/32595
Authors
Kemeny, S.
Shaw, T.
Nixon, R.
Fossum, E.
Date Acquired
August 23, 2013
Publication Date
June 9, 1994
Distribution Limits
Public
Copyright
Other
Keywords
VLSI route planning progammed terrain traversal time

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