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A Processor Interface Model for Fast System SimulationsThis paper presents an alternative technique for performing board level simulations of designs involving Processors. This technique requires only a standard.
Document ID
20060039067
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
hdl:2014/35454
Authors
Bolotin, G.
Date Acquired
August 23, 2013
Publication Date
September 21, 1993
Distribution Limits
Public
Copyright
Other
Keywords
alternative method for performing board level simulations board level
simulations processor interface model fast system simulations

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