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A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS TechnologyThis paper presents a low-power VLSI neural processor that has been developed for high-speed vision processing based upon the frequency-sensitive self-organization (FSO) neural algorithm.
Document ID
20060040840
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/18059
Authors
Fang, W. C.
Lin, T. H.
Date Acquired
August 23, 2013
Publication Date
January 1, 1999
Subject Category
Electronics And Electrical Engineering
Distribution Limits
Public
Copyright
Other
Keywords
VLSI Neural Processor Design High Speed Image Data Compression SOI CMOS
Technology

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