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Parallel VLSI equalizer architectures for multi-Gbps satellite communicationsThis paper provides an overview of a new very large scale integration (VLSI) architecture for implementing a frequency domain least-mean squares (LMS) complex equalizer.
Document ID
20060042422
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/36851
Authors
Ghuman, P.
Gray, A. A.
Hoy, S. D.
Date Acquired
August 23, 2013
Publication Date
November 25, 2001
Subject Category
Communications And Radar
Distribution Limits
Public
Copyright
Other
Keywords
pulse position modulation optical communications adaptive threshold receiver ROC

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