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Design and implementation of a structured LDPC decoder on FPGAWe present a design framework for the implementation for a Low-Density Parity-Check (LDPC) decoders. We employed a scalable decoding architecture for a certain class of structured LDPC codes.
Document ID
20060043518
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/38481
Authors
Lee, Jason Kwok-San
Lee, Benjamin
Thorpe, Jeremy
Andrews, Kenneth
Dolinar, Sam
Hamkins, Jon
Date Acquired
August 23, 2013
Publication Date
April 1, 2004
Meeting Information
Meeting: Symposium on Field Programmable Custom Computing Machines
Location: Napa, CA
Country: United States
Start Date: April 1, 2004
Distribution Limits
Public
Copyright
Other
Keywords
channel capacity
LDPC
error correcting codes

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