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Process for making a multilayer interconnect systemA process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.
Document ID
20080012209
Acquisition Source
Langley Research Center
Document Type
Other - Patent
Authors
Zachry, Clyde L.
Niedzwiecke, Andrew J.
Date Acquired
August 24, 2013
Publication Date
May 4, 1976
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Number: US-PATENT-3,953,924
Patent Application Number: US-PATENT-APPL-SN-591591
Funding Number(s)
CONTRACT_GRANT: NAS1-12435
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-3,953,924
Patent Application
US-PATENT-APPL-SN-591591

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