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Multinode reconfigurable pipeline computerA multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.
Document ID
20080012372
Acquisition Source
Langley Research Center
Document Type
Other - Patent
Authors
Nosenchuck, Daniel M.
Littman, Michael G.
Date Acquired
August 24, 2013
Publication Date
March 7, 1989
Subject Category
Computer Systems
Report/Patent Number
Patent Number: US-PATENT-4,811,214
Patent Application Number: US-PATENT-APPL-SN-931549
Funding Number(s)
CONTRACT_GRANT: NAG1-494
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-4,811,214
Patent Application
US-PATENT-APPL-SN-931549
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