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Network-Attached Solid-State Recorder ArchitectureA document discusses placing memory modules on the high-speed serial interconnect, which is used by a spacecraft s computer elements for inter-processor communications, to allow all multiple computer system architectures to access the spacecraft data storage at the same time. Each memory board is identical electrically and receives its bus ID upon connection to the system. The computer elements are configured in a similar fashion. The architecture allows for multiple memory boards to be accessed simultaneously by different computer elements, and results in a scalable, strong, fault-tolerant system. The IEEE-1393 ring bus can be routed so that multiple card failures can occur and the mass memory storage will still function.
Document ID
20080047219
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
Authors
Cox, Brian
(California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 24, 2013
Publication Date
November 1, 2008
Publication Information
Publication: NASA Tech Briefs, November 2008
Subject Category
Computer Operations And Hardware
Report/Patent Number
NPO-45204
Distribution Limits
Public
Copyright
Public Use Permitted.
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