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Ring Bus Architecture for a Solid-State RecorderA document concisely describes a ring bus architecture for a proposed solid-state recorder (SSR) that would serve as buffer of data to be transmitted from a spacecraft to Earth. This architecture would afford fault tolerance needed for reliable operation in an anticipated high-radiation environment in which traditional SSRs cannot operate reliably. Features of the architecture include one or more controller boards and multiple memory boards interconnected in a ringlike topology. The interconnections would be high-speed serial links complying with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus). Accordingly, each controller and memory board would be equipped with an IEEE-1393-compliant ring-bus-interface unit. The ringlike topology and the multiplicity of memory boards (and, optionally, of controller boards) would afford the redundancy needed for fault tolerance. Each board would be a fault-containment region. The IEEE 1393 links could be routed so that the SSR would continue to function even in the event of multiple failures. This architecture would also support scalability over a wide range. In a fully redundant configuration, it could accommodate between 1 and 125 memory boards.
Document ID
20090020482
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
Authors
Walker, W. John
(California Inst. of Tech. Pasadena, CA, United States)
Kopf, Edward
(California Inst. of Tech. Pasadena, CA, United States)
Cox, Brian
(California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 24, 2013
Publication Date
March 1, 2008
Publication Information
Publication: NASA Tech Briefs, March 2008
Subject Category
Man/System Technology And Life Support
Report/Patent Number
NPO-45132
Report Number: NPO-45132
Distribution Limits
Public
Copyright
Public Use Permitted.
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