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Systems and methods for detecting a failure event in a field programmable gate arrayAn embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.
Document ID
20090042856
Acquisition Source
Headquarters
Document Type
Other - Patent
Authors
Ng, Tak-Kwong
Herath, Jeffrey A.
Date Acquired
August 24, 2013
Publication Date
September 15, 2009
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Number: US-Patent-7,590,904
Patent Application Number: US-Patent-Appl-SN-11/531,703
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-7,590,904
Patent Application
US-Patent-Appl-SN-11/531,703
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