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Universal programmable logic gate and routing methodAn universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Document ID
20090043053
Acquisition Source
Headquarters
Document Type
Other - Patent
Authors
Fijany, Amir
Vatan, Farrokh
Akarvardar, Kerem
Blalock, Benjamin
Chen, Suheng
Cristoloveanu, Sorin
Kolawa, Elzbieta
Mojarradi, Mohammad M.
Toomarian, Nikzad
Date Acquired
August 24, 2013
Publication Date
April 7, 2009
Subject Category
Computer Programming And Software
Report/Patent Number
Patent Number: US-Patent-7,514,964
Patent Application Number: US-Patent-Appl-SN-11/377,935
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-7,514,964
Patent Application
US-Patent-Appl-SN-11/377,935
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