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Computationally efficient modeling and simulation of large scale systemsA method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.
Document ID
20100040686
Acquisition Source
Ames Research Center
Document Type
Other - Patent
Authors
Jain, Jitesh
Cauley, Stephen F.
Li, Hong
Koh, Cheng-Kok
Balakrishnan, Venkataramanan
Date Acquired
August 24, 2013
Publication Date
August 10, 2010
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Patent Application Number: US-Patent-Appl-SN-11/593,465
Patent Number: US-Patent-7,774,725
Funding Number(s)
CONTRACT_GRANT: NCC2-1363
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-7,774,725
Patent Application
US-Patent-Appl-SN-11/593,465
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