Capacitors with low equivalent series resistance

An electric double layer capacitor (EDLC) in a coin or button cell configuration having low equivalent series resistance (ESR). The capacitor comprises mesh or other porous metal that is attached via conducting adhesive to one or both the current collectors. The mesh is embedded into the surface of the adjacent electrode, thereby reducing the interfacial resistance between the electrode and the current collector, thus reducing the ESR of the capacitor.