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Scalable Multiprocessor for High-Speed Computing in SpaceA report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.
Document ID
20110020299
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
Authors
Lux, James
(California Inst. of Tech. Pasadena, CA, United States)
Lang, Minh
(California Inst. of Tech. Pasadena, CA, United States)
Nishimoto, Kouji
(California Inst. of Tech. Pasadena, CA, United States)
Clark, Douglas
(California Inst. of Tech. Pasadena, CA, United States)
Stosic, Dorothy
(California Inst. of Tech. Pasadena, CA, United States)
Bachmann, Alex
(California Inst. of Tech. Pasadena, CA, United States)
Wilkinson, William
(California Inst. of Tech. Pasadena, CA, United States)
Steffke, Richard
(California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 25, 2013
Publication Date
October 1, 2004
Publication Information
Publication: NASA Tech Briefs, October 2004
Subject Category
Computer Operations And Hardware
Report/Patent Number
NPO-40270
Report Number: NPO-40270
Distribution Limits
Public
Copyright
Public Use Permitted.
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