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Aeroflex Technology as Class-Y DemonstratorModern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.
Document ID
20150000446
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other
Authors
Suh, Jong-ook
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Agarwal, Shri
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Popelar, Scott
(Aeroflex, Inc. Colorado Springs, CO, United States)
Date Acquired
January 15, 2015
Publication Date
September 1, 2014
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
JPL-Publ-14-16
Report Number: JPL-Publ-14-16
Funding Number(s)
WBS: WBS 40.49.02.12
WBS: WBS 724297.40.49.11
WBS: WBS 104593
CONTRACT_GRANT: NAS7-03001
Distribution Limits
Public
Copyright
Public Use Permitted.
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