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Computationally Efficient Modeling and Simulation of Large Scale SystemsA system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.
Document ID
20150003306
Acquisition Source
Ames Research Center
Document Type
Other - Patent
Authors
Jain, Jitesh
Cauley, Stephen F
Li, Hong
Koh, Cheng-Kok
Balakrishnan, Vankataramanan
Date Acquired
March 19, 2015
Publication Date
June 3, 2014
Subject Category
Numerical Analysis
Electronics And Electrical Engineering
Report/Patent Number
Patent Application Number: US-Patent-Appl-SN-13/710,145
Patent Number: US-Patent-8,745,563
Funding Number(s)
CONTRACT_GRANT: NSF-CCR-0203362
CONTRACT_GRANT: NSF-CCR-9984553
CONTRACT_GRANT: USAF-FA8650-04-D-2409
CONTRACT_GRANT: NCC2-1363
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-Patent-8,745,563
Patent Application
US-Patent-Appl-SN-13/710,145
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