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2nd Generation QUATARA Flight Computer ProjectSingle core flight computer boards have been designed, developed, and tested (DD&T) to be flown in small satellites for the last few years. In this project, a prototype flight computer will be designed as a distributed multi-core system containing four microprocessors running code in parallel. This flight computer will be capable of performing multiple computationally intensive tasks such as processing digital and/or analog data, controlling actuator systems, managing cameras, operating robotic manipulators and transmitting/receiving from/to a ground station. In addition, this flight computer will be designed to be fault tolerant by creating both a robust physical hardware connection and by using a software voting scheme to determine the processor's performance. This voting scheme will leverage on the work done for the Space Launch System (SLS) flight software. The prototype flight computer will be constructed with Commercial Off-The-Shelf (COTS) components which are estimated to survive for two years in a low-Earth orbit.
Document ID
20150009456
Acquisition Source
Marshall Space Flight Center
Document Type
Other
Authors
Falker, Jay
(NASA Headquarters Washington, DC United States)
Keys, Andrew
(NASA Marshall Space Flight Center Huntsville, AL, United States)
Fraticelli, Jose Molina
(NASA Marshall Space Flight Center Huntsville, AL, United States)
Capo-Iugo, Pedro
(NASA Marshall Space Flight Center Huntsville, AL, United States)
Peeples, Steven
(NASA Marshall Space Flight Center Huntsville, AL, United States)
Date Acquired
June 3, 2015
Publication Date
March 31, 2015
Subject Category
Computer Operations And Hardware
Report/Patent Number
M15-4504
Report Number: M15-4504
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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