Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal InterconnectThe fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.
Document ID
20150023024
Acquisition Source
Glenn Research Center
Document Type
Presentation
Authors
Spry, David J. (NASA Glenn Research Center Cleveland, OH United States)
Neudeck, Philip G. (NASA Glenn Research Center Cleveland, OH United States)
Chen, Liangyu (Ohio Aerospace Inst. Brook Park, OH, United States)
Evans, Laura J. (NASA Glenn Research Center Cleveland, OH United States)
Lukco, Dorothy (Vantage Partners, LLC Brook Park, OH, United States)
Chang, Carl W. (Vantage Partners, LLC Brook Park, OH, United States)
Beheim, Glenn M. (NASA Glenn Research Center Cleveland, OH United States)
Date Acquired
December 15, 2015
Publication Date
October 4, 2015
Subject Category
Electronics And Electrical EngineeringSolid-State Physics
Report/Patent Number
GRC-E-DAA-TN27167
Meeting Information
Meeting: International Conference on Silicon Carbide and Related Materials