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Chip Scale Package Implementation ChallengesThe JPL-led MicrotypBGA Consortium of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Document ID
20210002718
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other
External Source(s)
hdl:2014/16787
Authors
Ghaffarian, R.
Date Acquired
June 1, 1999
Publication Date
June 1, 1999
Publication Information
Publisher: UNKNOWN
Distribution Limits
Public
Copyright
Other
Technical Review
Keywords
chipscale
package
CSP
isothermal
aging
thermal
cycling
solder
joint
reliability
BGA
shear
force

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