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A Novel 3D DRAM Memory Cube Architecture for Space ApplicationsThe first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.
Document ID
20210008276
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Yang-Scharlotta, Jean
Lim, Sung Kyu
Carson, John
Krutzik, Christian
Yamaguchi, James
Sidana, Amanvir
Agnesina, Anthony
Date Acquired
June 24, 2018
Publication Date
June 24, 2018
Publication Information
Publisher: Pasadena, CA: Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2018
Distribution Limits
Public
Copyright
Other
Technical Review

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