Parallelized Convolutional Interleaver Implementation for Efficient DDR Memory Access

Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.