Optimizing Thin Cover Layers for Optically Clear Electrodynamic Dust Shields

This project looked at optimizing the dielectric cover layer on top of an optically clear glass electrodynamic dust shield (EDS). The EDS is a device that uses high voltage electric fields to remove dust from surfaces. Currently, the EDS uses 2000 volts to remove dust, but by optimizing the cover layer and the geometry of the EDS, this voltage can be lowered to improve safety and reduce electromagnetic interference (EMI) and the complexity of supporting systems. This project was able to demonstrate successful dust clearing on an EDS with 750 volts in high vacuum (~1E-5 torr) conditions. The EDS had a trace spacing of 500 μm, and the Parylene C cover layer had a thickness of 25 μm. There is still a substantial amount of room for improvement of these devices, which may be able to push the operating voltage even lower.