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Phase-locked loopsThe basic analysis and design procedures are described for the realization of analog phase-locked loops (APLL), hybrid phase-locked loops (HPLL), discrete phase-locked loops, and digital phase-locked loops (DPLL). Basic configurations are diagrammed, and performance curves are given. A discrete communications model is derived and developed. The use of the APLL as an optimum angle demodulator and the Kalman-Bucy approach to APLL design are discussed. The literature in the area of phase-locked loops is reviewed, and an extensive bibliography is given. Although the design of APLLs is fairly well documented, work on discrete, hybrid, and digital PLLs is scattered, and more will have to be done in the future to pinpoint the formal design of DPLLs.
Document ID
19740057291
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Gupta, S. C.
(Southern Methodist University Dallas, Tex., United States)
Date Acquired
August 7, 2013
Publication Date
January 1, 1974
Subject Category
Communications
Meeting Information
Meeting: Communication Systems and Technology Conference
Location: Dallas, TX
Start Date: April 30, 1974
End Date: May 1, 1974
Accession Number
74A40041
Funding Number(s)
CONTRACT_GRANT: NGR-44-007-049
Distribution Limits
Public
Copyright
Other

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