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Formulation of a methodology for power circuit design optimizationA methodology for optimizing power-processor designs is described which achieves optimization with respect to some power-processor characteristic deemed particularly desirable by the designer, such as weight or efficiency. Optimization theory based on Lagrange multipliers is reviewed together with nonlinear programming techniques employing penalty functions. The methodology, the task of which is to minimize an objective function subject to design constraints, is demonstrated with the aid of four examples: optimum-weight core selection for an inductor with a predetermined winding size, optimum-weight inductor design with a given loss constraint, optimum-loss inductor design with a given weight constraint, and a comparison of optimum-weight single- and two-stage input-filter designs with identical loss and other requirement constraints. Closed-form solutions for the first three examples are obtained by applying the Lagrange-multiplier method, but solutions for the last example are found numerically through the use of the sequential unconstrained minimization technique.
Document ID
19770058101
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Yu, Y.
(TRW Defense and Space Systems Group Redondo Beach, CA, United States)
Bachmann, M.
(TRW Defense and Space Systems Group Redondo Beach, CA, United States)
Lee, F. C. Y.
(TRW Defense and Space Systems Group Redondo Beach, Calif., United States)
Triner, J. E.
(NASA Lewis Research Center Cleveland, Ohio, United States)
Date Acquired
August 9, 2013
Publication Date
January 1, 1976
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: Power Electronics Specialists Conference
Location: Cleveland, OH
Start Date: June 8, 1976
End Date: June 10, 1976
Accession Number
77A40953
Funding Number(s)
CONTRACT_GRANT: NAS3-19690
Distribution Limits
Public
Copyright
Other

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