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Strobe-margin test for plated memory systemsTechnique measures performance of plated-wire memories. Strobe-margin test (SMT) utilizes worst-case testing and automatically gives exact strobe margin. Test is automatic; thus, memory system-level test is superior to tests at component level that use artificial test conditions. Test is significant tool in design and test of plated-wire memory systems. It can rapidly quantify memory-system margin on each production unit and impact of any design changes.
Document ID
19780000154
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Anspach, T. E.
(Honeywell, Inc.)
Clarke, J. W.
(Honeywell, Inc.)
Constable, R. C.
(Honeywell, Inc.)
Date Acquired
August 9, 2013
Publication Date
October 1, 1978
Publication Information
Publication: NASA Tech Briefs
Volume: 3
Issue: 2
ISSN: 0145-319X
Subject Category
Electronic Components And Circuits
Report/Patent Number
MFS-23838
Accession Number
78B10154
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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