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analyzing cmos/sos fabrication for lsi arraysReport discusses set of design rules that have been developed as result of work with test arrays. Set of optimum dimensions is given that would maximize process output and would correspondingly minimize costs in fabrication of large-scale integration (LSI) arrays.
Document ID
19780000158
Document Type
Other - NASA Tech Brief
Authors
Ipri, A. C.
(RCA Corp.)
Date Acquired
August 9, 2013
Publication Date
October 1, 1978
Publication Information
Publication: NASA Tech Briefs
Volume: 3
Issue: 2
ISSN: 0145-319X
Subject Category
ELECTRONIC COMPONENTS AND CIRCUITS
Report/Patent Number
MFS-23788
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.