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Implementation of real-time digital signal processing systemsSpecial purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.
Document ID
19790044037
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Narasimha, M.
(Stanford Univ. CA, United States)
Peterson, A.
(Stanford Univ. CA, United States)
Narayan, S.
(Stanford University Stanford, Calif., United States)
Date Acquired
August 9, 2013
Publication Date
January 1, 1978
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: Real-time signal processing; Seminar
Location: San Diego, CA
Start Date: August 28, 1978
End Date: August 29, 1978
Accession Number
79A28050
Funding Number(s)
CONTRACT_GRANT: N00014-75-C-0601
CONTRACT_GRANT: NGL-05-020-014
Distribution Limits
Public
Copyright
Other

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