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Methodology for measurement of fault latency in a digital avionic miniprocessorInvestigations regarding the synthesis of a reliability assessment capability for fault-tolerant computer-based systems have been conducted for several years. In 1978 a pilot study was conducted to test the feasibility of measuring detection coverage and investigating the dynamics of fault propagation in a digital computer. A description is presented of an investigation concerned with the applicability of previous results to a real avionics processor. The obtained results show that emulation is a practicable approach to failure modes and effects analysis of a digital processor. The run time of the emulated processor on a PDP-10 host computer is only 20,000 to 25,000 times slower than the actual processor. As a consequence large numbers of faults can be studied at relatively little cost and in a timely manner.
Document ID
19820029958
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Mcgough, J. G.
(Bendix Corp. Teterboro, NJ, United States)
Swern, F.
(Bendix Corp. Flight Systems Div., Teterboro, NJ, United States)
Bavuso, S. J.
(NASA Langley Research Center Hampton, VA, United States)
Date Acquired
August 10, 2013
Publication Date
January 1, 1981
Subject Category
Computer Operations And Hardware
Report/Patent Number
AIAA PAPER 81-2282
Meeting Information
Meeting: In: Digital Avionics Systems Conference
Location: St. Louis, MO
Start Date: November 17, 1981
End Date: November 19, 1981
Accession Number
82A13493
Funding Number(s)
CONTRACT_GRANT: NAS1-15946
Distribution Limits
Public
Copyright
Other

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