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Massively parallel processor computerAn apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.
Document ID
19830017107
Acquisition Source
Legacy CDMS
Document Type
Other - Patent
Authors
Fung, L. W.
(NAS-NRC Washington, D.C., United States)
Date Acquired
September 4, 2013
Publication Date
April 12, 1983
Subject Category
Computer Operations And Hardware
Report/Patent Number
Patent Application Number: US-PATENT-APPL-SN-041143
Patent Number: US-PATENT-4,380,046
Patent Number: NASA-CASE-GSC-12223-1
Accession Number
83N25378
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-4,380,046|NASA-CASE-GSC-12223-1
Patent Application
US-PATENT-APPL-SN-041143
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