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A fast, programmable hardware architecture for spaceborne SAR processingThe launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.
Document ID
19840008341
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Bennett, J. R.
(MacDonald Dettwiler and Associates Ltd., Richmond British Columbia, Canada)
Cumming, I. G.
(MacDonald Dettwiler and Associates Ltd., Richmond British Columbia, Canada)
Lim, J.
(MacDonald Dettwiler and Associates Ltd., Richmond British Columbia, Canada)
Wedding, R. M.
(MacDonald Dettwiler and Associates Ltd., Richmond British Columbia, Canada)
Date Acquired
August 12, 2013
Publication Date
July 1, 1983
Publication Information
Publication: JPL Spaceborne Imaging Radar Symp.
Subject Category
Communications And Radar
Accession Number
84N16409
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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