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A validation methodology for fault-tolerant clock synchronizationA validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating an experimental implementation of the Software Implemented Fault Tolerance (SIFT) clock synchronization algorithm. The design proof of the algorithm defines the maximum skew between any two nonfaulty clocks in the system in terms of theoretical upper bounds on certain system parameters. The quantile to which each parameter must be estimated is determined by a combinatorial analysis of the system reliability. The parameters are measured by direct and indirect means, and upper bounds are estimated. A nonparametric method based on an asymptotic property of the tail of a distribution is used to estimate the upper bound of a critical system parameter. Although the proof process is very costly, it is extremely valuable when validating the crucial synchronization subsystem.
Document ID
Document Type
Conference Paper
Johnson, S. C.
(NASA Langley Research Center Hampton, VA, United States)
Butler, R. W.
(NASA Langley Research Center Hampton, VA, United States)
Date Acquired
August 12, 2013
Publication Date
January 1, 1984
Subject Category
Computer Systems
Report/Patent Number
AIAA PAPER 84-2648
Meeting Information
Digital Avionics Systems Conference(Baltimore, MD)
Accession Number
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