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VLSI Architectures for Computing DFT'sSimplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.
Document ID
19860000324
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Truong, T. K.
(Caltech)
Chang, J. J.
(Caltech)
Hsu, I. S.
(Caltech)
Reed, I. S.
(Caltech)
Pei, D. Y.
(Caltech)
Date Acquired
August 12, 2013
Publication Date
July 1, 1986
Publication Information
Publication: NASA Tech Briefs
Volume: 10
Issue: 4
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-16656
Accession Number
86B10324
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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