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MOS integrated circuit fault modelingThree digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
Document ID
19860019793
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Sievers, M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 12, 2013
Publication Date
June 1, 1985
Publication Information
Publication: Product Assurance Technology for Custom LSI(VLSI Electronics
Subject Category
Electronics And Electrical Engineering
Accession Number
86N29265
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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