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Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chipsA detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
Document ID
19870034743
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Zoutendyk, J. A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Smith, L. S.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Soli, G. A.
(California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Smith, S. L.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Atwood, G. E.
(Intel Corp. Santa Clara, CA, United States)
Date Acquired
August 13, 2013
Publication Date
December 1, 1986
Publication Information
Publication: IEEE Transactions on Nuclear Science
Volume: NS-33
ISSN: 0018-9499
Subject Category
Electronics And Electrical Engineering
Accession Number
87A22017
Distribution Limits
Public
Copyright
Other

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