NTRS - NASA Technical Reports Server

Back to Results
Measurement-based analysis of error latencyThis paper demonstrates a practical methodology for the study of error latency under a real workload. The method is illustrated with sampled data on the physical memory activity, gathered by hardware instrumentation on a VAX 11/780 during the normal workload cycle of the installation. These data are used to simulate fault occurrence and to reconstruct the error discovery process in the system. The technique provides a means to study the system under different workloads and for multiple days. An approach to determine the percentage of undiscovered errors is also developed and a verification of the entire methodology is performed. This study finds that the mean error latency, in the memory containing the operating system, varies by a factor of 10 to 1 (in hours) between the low and high workloads. It is found that of all errors occurring within a day, 70 percent are detected in the same day, 82 percent within the following day, and 91 percent within the third day. The increase in failure rate due to latency is not so much a function of remaining errors but is dependent on whether or not there is a latent error.
Document ID
Document Type
Reprint (Version printed in journal)
Chillarege, Ram
(IBM Thomas J. Watson Research Center Yorktown Heights, NY, United States)
Iyer, Ravishankar K.
(Illinois, University Urbana, United States)
Date Acquired
August 13, 2013
Publication Date
May 1, 1987
Publication Information
Publication: IEEE Transactions on Computers
Volume: C-36
ISSN: 0018-9340
Subject Category
Computer Systems
Accession Number
Funding Number(s)
CONTRACT_GRANT: N00014-84-C-0149
Distribution Limits

Available Downloads

There are no available downloads for this record.
No Preview Available