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Addressable Inverter Matrix Tests Integrated-Circuit WaferAddressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.
Document ID
19880000073
Document Type
Other - NASA Tech Brief
Authors
Buehler, Martin G. (Caltech)
Date Acquired
August 13, 2013
Publication Date
February 1, 1988
Publication Information
Publication: NASA Tech Briefs
Volume: 12
Issue: 2
ISSN: 0145-319X
Subject Category
ELECTRONIC COMPONENTS AND CIRCUITS
Report/Patent Number
NPO-16612
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.